df-x8/1

Architecture

Registers

• PC (Program Counter): Holds the address of the next instruction.
• MA (Memory Address): Holds memory addresses during access.
• MB (Memory Buffer): Holds data being transferred to/from memory.
• AC (Accumulator): Main arithmetic register.
• Link (L): Single-bit register used to store carry/borrow during arithmetic operations and extended shifts.
• Quotient (MQ): Register used in multiplication and division operations to hold intermediate and final quotient values.
• IR (Instruction Register): Holds the current instruction.

Memory

The machine uses a 4K memory space. Each memory location stores a 12-bit word. Locations are grouped in 32 pages of 128 words.

Instruction Format

A 12-bit word is structured as follows:

[ OPCODE (3 bits) | I (1 bit) | Z/C (1 bit) | ADDRESS (7 bits) ]

• OPCODE: Defines the instruction type.
• I: Indirect addressing flag.
• Z/C: Zero page or current page selection.
• ADDRESS: Memory address field.

Instruction Cycle

The execution of an instruction follows three main steps:

1. Fetch: The instruction at the address in PC is loaded into IR.
2. Decode: The opcode is extracted from IR. Addressing is resolved.
3. Execute: The instruction is performed.

Addressing Modes

• Direct: The address field points directly to the operand.
• Indirect: The address field points to a memory location containing the operand address.

Instruction Set

MRI (Memory Reference Instructions)

• AND: AC ← AC AND M[EA]
• TAD (Two's Complement Add): AC ← AC + M[EA]
  If there's a carry, the Link is complemented.
• Increment and Skip if Zero (ISZ): M[EA] ← M[EA] + 1
  If resultant content equal zero, the contents of the PC are incremented by one, skipping the next instruction.
• DCA (Deposit and Clear AC): AC → M[EA] then 0 → AC
• JMS (Jump to Subroutine): PC → M[EA] then M[EA + 1] → PC
• JMP: M[EA] → PC
• IOT: The content of M[EA] is send to the console as ASCII.
• OPR: Any logical combination of bits within these groups can be combined into one micro instructions.
  • OPR1

    | OP 7      |   |CLA|   |CMA|   |Rot R  |Rot if
    [ 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 ]
                | 0 |   |CLL|   |CML|   |Rot L   |IAC

    Logical Sequence:
    1. CLA, CLL
    2. CMA, CML
    3. IAC
    4. RAR, RAL, RTR, RTL
    • NOP: causes one cycle delay
    • IAC:
    AC + 1 → AC
    • RAL (Rotate AC Left):ACj → ACj - 1, AC0 → L, L → AC11
    • RTL (Rotate Two Left):ACj → ACj - 2, AC1 → L, AC0 → AC11, L → AC10
    • RAR (Rotate AC Right):ACj → ACj + 1, L → AC0, AC11 → L
    • RTR (Rotate Two Right):ACj → ACj + 2, L → AC1, AC11 → AC0, AC10 → L
    • CML (Complement Link):!L → L
    • CMA (Complement AC):!AC → AC (each bit is complemented individually)
    • CIA (Complement and Increment AC): CMA then IAC
    • CLL (Clear Link):0 → L
    • STL (Set Link): 1 → L
    • CLA (Clear AC):0 → AC
    • STA (Set AC):1 → ACj
  • OPR2 If Skips are combined in a single instruction, the inclusion OR of the conditions determines the Skip when Bit 8 = 0;
    the AND of the inverse of the conditions determines the Skip when Bit 8 = 1.

    | OP 7      |   |CLA|   |SZA|   |S--|   |HLT |
    [ 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 ]
                | 1 |   |SMA|   |SNL|   |OSR|    |0

    Logical Sequence:
    1. Bit 8 = 0: Either SMA OR SZA OR SNL
    2. Bit 8 = 1: Both SPA AND SNA AND SZL
    3. CLA
    4. OSR, HLT
    if Bit 7 and Bit 0: SNL
    • HLT:Stop at the end of the current machine cycle
    • OSR (OR Switch Register):ACj OR SRj → ACj
    • SKP (Skip, unconditionnal): 111100001000 PC + 1 → PC
    • SNL (Skip on Non-zero Link): 111100010000if L = 1 then PC + 1 → PC
    • SZL (Skip on Zero Link): 111100011000if L = 0 then PC + 1 → PC
    • SZA (Skip on Zero AC): 111100100000if AC = 0 then PC + 1 → PC
    • SNA (Skip on Non-zero AC): 111100101000if AC != 0 then PC + 1 → PC
    • SMA (Skip on Minus AC): 111101000000if AC0 = 1 then PC + 1 → PC
    • SPA (Skip on Positive AC): 111101001000if AC0 = 0 then PC + 1 → PC
    • CLA (Clear AC): 1111100000000 → AC